题目： High Speed Interconnect Modeling, Measurement, and Correlation

时间：2015年6月4日（星期四），下午1:30-4:30

地点：玉泉校区，行政楼108会议室

报告人：Xiaoning Ye

专家介绍

Xiaoning Ye is currently a Principal Engineer at Intel Corporation, working on signal integrity of high speed interconnects in Server systems. He received his Bachelor and Master Degrees in electronics engineering from Tsinghua University, Beijing, China, in 1995 and 1997 respectively, and Ph.D. degree in electrical engineering from University of Missouri – Rolla (currently Missouri University of Science and Technology) in 2000. He has published over 50 IEEE and other technical papers, and holds 6 patents and several patent applications. Xiaoning was chair of TC10 (signal integrity and power integrity) of EMC society during 2012-2014, and is currently secretary of Technical Advisory Committee of EMC society.

报告内容

High speed links are running at micro-wave frequencies and high quality models are essential to the IO design. In this presentation, the author will discuss modeling challenges and provide simulation guidelines in building accurate electrical models of link components such as PCB, package, connector, etc. In-depth analysis of the PCB technology will be provided to reveal why traditional PCB modeling methodology is running out of steam at multi-GHz frequencies.  The presentation will also address another critical aspect of high speed interconnect design: the simulation and measurement correlation.  Practical examples using TDR/VNA to perform simulation/measurement correlation will be given in the presentation.