At 3 pm on March 14, 2018, Prof. Sharon Hu made a report on the topic of “A Cross-Layer Perspective for Hardware Accelerator Design --- From beyond-COMS device to deep learning” in 111 Administrative Building. Sharon Hu is a professor at the School of Computer Science and Engineering of the University of Notre Dame, and IEEE Fellow.
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At the beginning of the lectutre, Professor Hu first introduced the 0.3uJ/op energy efficiency challenge proposed by the U.S. Department of Defense, introduced the comparison of the energy efficiency of different existing hardware accelerators with the MNIST test as an example, and outlined the difficulties that need to be overcome to accomplish this challenge. With the system design flow as an outline, Professor Hu introduced how the team under the leadership of her implemented the design and test procedure of MNIST handwritten character detection by adopting a CeNN structure with better performance on non-CMOS devices in order to achieve this challenge.
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In the lecture, Prof. Hu introduced some of the design difficulties and key details of constructing a convolutional neural network using the CeNN structure step by step, and how to optimize the system performance and have better results through various adjustments in aspects such as hardware structure, system design, and software algorithms. The overall planning idea has benefited the audience a lot.
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After the academic lecture, teachers and students discussed in depth with Professor Hu on the issues of chip system design, manufacturing and testing, etc. The academic atmosphere was very strong then. At the end of the lecturte, Prof. Hu briefly introduced the University of Notre Dame and the attractive doctoral students and summer exchange programs of the School of Computer Science and Engineering, and encouraged the students to go for further studies in the University of Notre Dame.
